With the recent progress of highly integrated design of a semiconductor integrated circuit, density of a wiring pattern has increased, and a wiring has become longer. Al was conventionally used for a wiring material; however, wiring delay has come up as a problem with the miniaturization of the wiring pattern. Recently, Cu is mainly used as a wiring material in order to solve the problem. However, it is difficult to transfer a wiring pattern on Cu itself unlike Al. Therefore, when a Cu wiring is formed, a damascene method for transferring a wiring trench pattern on an interlayer insulating film and for forming the wiring pattern thereon by embedding Cu is effective. Furthermore, the damascene method is classified into a single damascene method for separately forming Cu in a trench and Cu in a via, and a dual damascene method for simultaneously forming a trench and a via.
However, in a conventional damascene method, either of a single damascene method and a dual damascene method, sometimes sufficient yield is not obtained under the influence of particles generated in the process.
Patent Document 1
Japanese Patent Application Laid-open No. Hei 6-3 14679
Patent Document 2
Japanese Patent Application Laid-open No. 2001-44 167
Patent Document 3
Japanese Patent Application Laid-open No. Hei 3-6 8141